The present invention generally relates to computer logic system testing and, more particularly, to AC self-testing of logic systems utilized in, for example, large, complex digital computer systems implemented with high density, large scale integrated circuits.
The design and manufacture of integrated circuits which are free of design and reliability problems is a challenging task. It is standard practice to test integrated circuits for xe2x80x9chardxe2x80x9d functional failures as well as propensities to reliability problems. Such device testing is critical for identifying, analyzing, and correcting problem areas early.
Today, the Giga-Hertz era is beginning, and testing the timing critical paths at wafer level has become an important objective. Traditional wafer tests include flush testing, scan ring testing, DC stuck fault testing, random pattern testing, etc., all of which are conducted at low frequencies. For example, reference: Eichelberger et al., xe2x80x9cA Logic Design Structure for LSI Testability,xe2x80x9d Proceedings of the 14th Design Automation Conference, New Orleans, pp. 462-468 (1977); and Foote et al., xe2x80x9cTesting the 400 MHz IBM Generation-4 CMOS Chip,xe2x80x9d Proceedings of the International Test Conference 1997, Washington, D.C., pp. 106-114.
Screening out integrated circuit chips with timing problems has become essential as the number of integrated circuit chips which would pass low frequency testing but fail high frequency testing continues to increase Therefore, a means to perform an AC self-test on an integrated circuit, even at wafer level, has become more important.
One strategy for performing AC self-testing of a logic system would be as follows. A logic chip is first scanned with a set of pseudo-random data into its L1-latches by means of pulsing alternately the A-clock and the C2-clock (also known as the B-clock) in a known manner. The alternate pulsing is followed by a single pair of C2-clock and C1-clock signals at operating frequency. The single C2-clock pulse launches the scanned-in data through all timing paths, including the critical ones. The launched data is then captured by the subsequent single C1 clock pulse. If the data arrives on time, the C1 clock pulse will capture the data correctly. Data integrity is then checked by scanning out the captured data through alternating A-clock and B-clock pulses. Thus, the problem of doing AC testing is a challenge of designing a timing controller which generates a single pair of C1 and C2 clock pulses at operating speed. The present invention is directed to meeting this need without requiring a starting and stopping of the continuous clock signal driving the logic system.
Briefly summarized, provided herein is a clock controller which includes means for generating two overlapping pulses from a single continuous clock signal and a single DC input signal, as well as means for shaping the two overlapping pulses. The means for generating is responsive to the single DC input signal going high, and the means for shaping shapes the two overlapping pulses to produce two non-overlapping pulses at clock speed. The two non-overlapping clock pulses at clock speed comprise a single pair of clock pulses, C1 and C2, which can be used in performing AC testing of the logic system.
In another aspect, a clock controller for generating a single pair of clock pulses is provided. This clock controller includes latch circuitry and waveform shaper circuitry. The latch circuitry has a DC input signal connected to a data input, and a pair of continuous out-of-phase clock signals connected to capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses. The waveform shaper circuitry is connected to receive the two overlapping pulses and produce therefrom two non-overlapping pulses. The two non-overlapping pulses comprise a single pair of clock pulses, C1 and C2, approximately at clock speed of a logic system to be tested. The clock controller produces the single pair of clock pulses from the DC input signal and the pair of continuous out-of-phase clock signals.
In still another aspect, a method for generating a single pair of clock pulses is presented. The method includes: generating two overlapping pulses from a single continuous clock signal and a single DC input signal, the generating being responsive to the single DC input signal going high; and shaping the two overlapping pulses to produce two non-overlapping pulses at clock speed, the two non-overlapping pulses at clock speed comprising a single pair of clock pulses, wherein the single pair of clock pulses is useful in AC self-testing a logic system driven by the single continuous clock signal without requiring discontinuance of the single continuous clock signal.
In a further aspect, a method of AC self-testing a logic system is presented. This method includes: scanning a set of data into at least some latches of the logic system; generating a single pair of clock pulses at operating frequency without gating off an oscillator used to drive the logic system; and employing the single pair of clock pulses to launch scanned in data from a first set of latches and capture the data at a second set of latches of the logic system.
To restate, presented herein is a novel clock controller and clock generation method which produces a single pair of pulses at clock speed without requiring manipulation of the clock signal gating a logic system to be tested. The generation of the non-overlapping clock pulse-pair is used to perform a single step AC test and can be accomplished on chip, i.e., on the logic chip to be tested. No external gating of the oscillator driving the chip is required. This is significant because using external equipment to turn on and off the oscillator input pin may produce a pulse pair with distorted waveforms due to the existence of a relatively long cable that feeds the chip from the external clock source. Any distorted waveforms of the pulse-pair would give rise to erroneous measurement of the AC speed and hence defeat the purpose of the AC testing of the logic system. In accordance with the present invention, the pulse-pair is generated similar to the clock pulses in a real chip functional operation.
The basic structure of the xe2x80x9cclock splitters and registersxe2x80x9d infrastructure remains intact without being disturbed by the embedding of AC test logic in accordance with the present invention. The clock control and testing scheme of the present invention is totally transparent to logic designers and somewhat transparent to the clock tree designers. Only the chip integrator and physical layout engineer need to be concerned with the insertion of the logic for the present invention into the chip. This has an advantage from a design methodology point of view.
In addition, the DC RELEASE signal inputted to the clock controller logic is not timing critical. The positive-going transition of the RELEASE signal triggers the generation of a pulse-pair. This non-critically is significant because the pulse-pair generated is independent of how the RELEASE signal is raised. The waveform of the internal RELEASE (output of Latch 1 of FIG. 4) is not affected by the rise time of the external RELEASE signal (DIN of Latch 1 of FIG.4).
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.